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cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05490 rev. *d revised march 30, 2007 cy62157ev18 mobl ? 8-mbit (512k x 16) static ram features ? very high speed: 55 ns ? wide voltage range: 1.65v?2.25v ? pin compatible with cy62157dv18 and cy62157dv20 ? ultra low standby power ? typical standby current: 2 a ? maximum standby current: 8 a ? ultra low active power ? typical active current: 1.8 ma @ f = 1 mhz ? easy memory expansion with ce 1 , ce 2 and oe features ? automatic power down when deselected ? cmos for optimum speed and power ? available in pb-free 48-ball vfbga package functional description [1] the cy62157ev18 is a high performance cmos static ram organized as 512k words by 16 bits. this device features advanced circuit design to provide ultra low active current. this is ideal for providing more battery life? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power do wn feature that significantly reduces power consumption when addresses are not toggling. the device can also be put into standby mode when deselected (ce 1 high or ce 2 low or both bhe and ble are high). the input and output pins (io 0 through io 15 ) are placed in a high impedance state when: ? deselected (ce 1 high or ce 2 low) ? outputs are disabled (oe high) ? both byte high enable and byte low enable are disabled (bhe , ble high) or ? write operation is active (ce 1 low, ce 2 high and we low). write to the device by taking chip enables (ce 1 low and ce 2 high) and write enable (we ) input low. if byte low enable (ble ) is low, then data from io pins (io 0 through io 7 ), is written into the location specified on the address pins (a 0 through a 18 ). if byte high enable (bhe ) is low, then data from io pins (io 8 through io 15 ) is written into the location specified on the address pins (a 0 through a 18 ). read from the device by taking chip enables (ce 1 low and ce 2 high) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory loca tion specified by the address pins appear on io 0 to io 7 . if byte high enable (bhe ) is low, then data from memory appears on io 8 to io 15 . see the ?truth table? on page 9 for a complete description of read and write modes. product portfolio product v cc range (v) speed (ns) power dissipation operating i cc , (ma) standby, i sb2 ( a) f = 1mhz f = f max min typ [2] max typ [2] max typ [2] max typ [2] max cy62157ev18 1.65 1.8 2.25 55 1.8 3 18 25 2 8 notes 1. for best practice recommendations, refer to the cypress application note ? system design guidelines ? located at http://www.cypress.com. 2. typical values are included for reference only and are no t guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25c. [+] feedback [+] feedback
cy62157ev18 mobl ? document #: 38-05490 rev. *d page 2 of 12 logic block diagram pin configuration [3] 512k x 16 ram array io 0 ?io 7 row decoder a 8 a 7 a 6 a 5 a 2 column decoder a 11 a 12 a 13 a 14 a 15 sense amps data in drivers oe a 4 a 3 io 8 ?io 15 we ble bhe a 16 a 0 a 1 a 17 a 9 bhe ble a 10 a 18 power down circuit ce 2 ce 1 ce 2 ce 1 note 3. nc pins are not connected on the die. we a 11 a 10 a 6 a 0 a 3 ce 1 io 10 io 8 io 9 a 4 a 5 io 11 io 13 io 12 io 14 io 15 v ss a 9 a 8 oe a 7 io 0 bhe ce 2 a 17 a 2 a 1 ble io 2 io 1 io 3 io 4 io 5 io 6 io 7 a 15 a 14 a 13 a 12 nc a 18 nc 3 26 5 4 1 d e b a c f g h a 16 nc v cc v cc v ss 48-ball vfbga top view [+] feedback [+] feedback
cy62157ev18 mobl ? document #: 38-05490 rev. *d page 3 of 12 maximum ratings exceeding maximum ratings may im pair the useful life of the device. these user guidelines are not tested. storage temperature ................................ ?65c to + 150c ambient temperature with power applied ......................... .................. ?55c to + 125c supply voltage to ground potential ...............................?0.2v to 2.45v (v ccmax + 0.2v) dc voltage applied to outputs in high-z state [4, 5] ..............?0.2v to 2.45v (v ccmax + 0.2v) dc input voltage [4, 5] ......... ?0.2v to 2.45v (v ccmax + 0.2v) output current into outputs (l ow) ............................ 20 ma static discharge voltage ......... .............. .............. .... > 2001v (in accordance with mil-std-883, method 3015) latch-up current ................................................... > 200 ma operating range device range ambient temperature v cc [6] cy62157ev18ll industrial ?40c to +85c 1.65v to 2.25v electrical characteristics (over the operating range) parameter description test conditions 55 ns unit min typ [2] max v oh output high voltage i oh = ?0.1 ma v cc = 1.65v 1.4 v v ol output low voltage i ol = 0.1 ma v cc = 1.65v 0.2 v v ih input high voltage v cc = 1.65v to 2.25v 1.4 v cc + 0.2v v v il input low voltage v cc = 1.65v to 2.25v ?0.2 0.4 v i ix input leakage current gnd < v i < v cc ?1 +1 a i oz output leakage current gnd < v o < v cc , output disabled ?1 +1 a i cc v cc operating supply current f = f max = 1/t rc v cc = v cc(max) i out = 0 ma cmos levels 18 25 ma f = 1 mhz 1.8 3 ma i sb1 automatic cepower down current?cmos inputs ce 1 > v cc ? 0.2v or ce 2 < 0.2v v in > v cc ? 0.2v, v in < 0.2v) f = f max (address and data only), f = 0 (oe , we , bhe and ble ), v cc = v cc(max) . 28 a i sb2 [7] automatic ce power down current?cmos inputs ce 1 > v cc ? 0.2v or ce 2 < 0.2v, v in > v cc ? 0.2v or v in < 0.2v, f = 0, v cc = v cc(max) . 28 a capacitance [8] parameter description test conditions max unit c in input capacitance t a = 25c, f = 1 mhz, v cc = v cc(typ) 10 pf c out output capacitance 10 pf notes 4. v il(min) = ?2.0v for pulse durations less than 20 ns. 5. v ih(max) = v cc + 0.5v for pulse durations less than 20 ns. 6. full device ac operation assumes a 100 s ramp time from 0 to v cc (min) and 200 s wait time after v cc stabilization. 7. only chip enable (ce ) and byte enables (bhe and ble ) need to be tied to cmos levels to meet the i sb2 spec. other inputs can be left floating. 8. tested initially and after any design or proce ss changes that may affect these parameters. [+] feedback [+] feedback
cy62157ev18 mobl ? document #: 38-05490 rev. *d page 4 of 12 thermal resistance [8] parameter description test conditions bga unit ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, two-layer printed circuit board 72 c/w jc thermal resistance (junction to case) 8.86 c/w ac test loads and waveforms parameters value unit r1 13500 ? r2 10800 ? r th 6000 ? v th 0.80 v data retention characteristics (over the operating range) parameter descrip tion conditions min typ [2] max unit v dr v cc for data retention 1.0 v i ccdr data retention current v cc = v dr , ce 1 > v cc ? 0.2v, ce 2 < 0.2v,v in > v cc ? 0.2v or v in < 0.2v 13 a t cdr [8] chip deselect to data retention time 0 ns t r [9] operation recovery time t rc ns data retention waveform [10] 3v v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns output v equivalent to: thevenin equivalent all input pulses r th r1 v cc(min) t cdr v dr > 1.0v data retention mode t r v cc(min) ce 1 or v cc bhe .ble ce 2 or notes 9. full device operation requires linear v cc ramp from v dr to v cc(min) > 100 s or stable at v cc(min) > 100 s. 10. bhe .ble is the and of both bhe and ble . deselect the chip by either disabling ch ip enable signals or by disabling both bhe and ble . [+] feedback [+] feedback
cy62157ev18 mobl ? document #: 38-05490 rev. *d page 5 of 12 switching characteristics (over the operating range) [11, 12 ] parameter description 55 ns unit min max read cycle t rc read cycle time 55 ns t aa address to data valid 55 ns t oha data hold from address change 10 ns t ace ce 1 low and ce 2 high to data valid 55 ns t doe oe low to data valid 25 ns t lzoe oe low to low-z [13] 5ns t hzoe oe high to high-z [13, 14] 18 ns t lzce ce 1 low and ce 2 high to low-z [13] 10 ns t hzce ce 1 high and ce 2 low to high-z [13, 14] 18 ns t pu ce 1 low and ce 2 high to power up 0 ns t pd ce 1 high and ce 2 low to power down 55 ns t dbe ble /bhe low to data valid 55 ns t lzbe [15] ble /bhe low to low-z [13] 10 ns t hzbe ble /bhe high to high-z [13, 14] 18 ns write cycle [16] t wc write cycle time 45 ns t sce ce 1 low and ce 2 high to write end 35 ns t aw address setup to write end 35 ns t ha address hold from write end 0 ns t sa address setup to write start 0 ns t pwe we pulse width 35 ns t bw ble /bhe low to write end 35 ns t sd data setup to write end 25 ns t hd data hold from write end 0 ns t hzwe we low to high-z [13, 14] 18 ns t lzwe we high to low-z [13] 10 ns notes 11. test conditions for all parameters other than tri-state parame ters assume signal transition time of 1v/ns or less, timing re ference levels of v cc(typ) /2, input pulse levels of 0 to v cc(typ) , and output loading of the specified i ol /i oh as shown in the ?ac test loads and waveforms? on page 4 . 12. ac timing parameters are subject to byte enable signals (bhe or ble ) not switching when chip is disabled. please see application note an13842 for furthe r clarification. 13. at any given temperature and voltage condition, t hzce is less than t lzce , t hzbe is less than t lzbe , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 14. t hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the output enters a high impedance state. 15. if both byte enables are toggl ed together, this value is 10 ns. 16. the internal write time of the memory is defined by the overlap of we , ce = v il , bhe and/or ble = v il , and ce 2 = v ih . all signals must be active to initiate a write and any of these signals can terminate a write by going in active. the data input setup and hold timing must be referenced to the edge of the signal that terminates the write. [+] feedback [+] feedback
cy62157ev18 mobl ? document #: 38-05490 rev. *d page 6 of 12 switching waveforms read cycle 1 (address transition controlled) [17, 18] read cycle 2 (oe controlled) [18, 19] previous data valid data valid rc t aa t oha t rc address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t pd t hzbe t lzbe t hzce t dbe oe ce 1 address ce 2 bhe /ble data out v cc supply current high i cc i sb impedance notes: 17. the device is continuously selected. oe , ce 1 = v il , bhe and/or ble = v il , and ce 2 = v ih . 18. we is high for read cycle. 19. address valid before or similar to ce 1 , bhe , ble transition low and ce 2 transition high. [+] feedback [+] feedback
cy62157ev18 mobl ? document #: 38-05490 rev. *d page 7 of 12 write cycle 1 (we controlled) [16, 20, 21] write cycle 2 (ce 1 or ce 2 controlled) [16, 20, 21] switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe valid data t bw note 22 ce 1 address ce 2 we data io oe bhe /ble t hd t sd t pwe t ha t aw t sce t wc t hzoe valid data t bw t sa note 22 ce 1 address ce 2 we data io oe bhe /ble notes: 20. data io is high impedance if oe = v ih . 21. if ce 1 goes high and ce 2 goes low simultaneously with we = v ih , the output remains in a high impedance state. 22. during this period, the ios are in output state and input signals must not be applied. [+] feedback [+] feedback
cy62157ev18 mobl ? document #: 38-05490 rev. *d page 8 of 12 write cycle 3 (we controlled, oe low) [21] write cycle 4 (bhe /ble controlled, oe low) [21] switching waveforms (continued) valid data t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe t bw note 22 ce 1 address ce 2 we data io bhe /ble t hd t sd t sa t ha t aw t wc valid data t bw t sce t pwe note 22 ce 1 address ce 2 we data io bhe /ble [+] feedback [+] feedback
cy62157ev18 mobl ? document #: 38-05490 rev. *d page 9 of 12 truth table ce 1 ce 2 we oe bhe ble inputs/outputs mode power h x x x x x high-z deselect/power down standby (i sb ) x l x x x x high-z deselect/power down standby (i sb ) x x x x h h high-z deselect/power down standby (i sb ) l h h l l l data out (io 0 ?io 15 ) read active (i cc ) l h h l h l data out (io 0 ?io 7 ); high-z (io 8 ?io 15 ) read active (i cc ) l h h l l h high-z (io 0 ?io 7 ); data out (io 8 ?io 15 ) read active (i cc ) l h h h l h high-z output disabled active (i cc ) l h h h h l high-z output disabled active (i cc ) l h h h l l high-z output disabled active (i cc ) l h l x l l data in (io 0 ?io 15 ) write active (i cc ) l h l x h l data in (io 0 ?io 7 ); high-z (io 8 ?io 15 ) write active (i cc ) l h l x l h high-z (io 0 ?io 7 ); data in (io 8 ?io 15 ) write active (i cc ) ordering information speed (ns) ordering code package diagram package type operating range 55 CY62157EV18LL-55BVXI 51 -85150 48-ball very fine pitch ball grid array (pb-free) industrial contact your local cypress sales represen tative for availability of these parts [+] feedback [+] feedback
document #: 38-05490 rev. *d page 10 of 12 ? cypress semiconductor corporation, 2006-2007. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent o r other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems wh ere a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufa cturer assumes all risk of such use and in doing so indemni fies cypress against all charges. cy62157ev18 mobl ? package diagrams figure 1. 48-ball vfbga (6 x 8 x 1 mm), 51-85150 mobl is a registered trademark, and more battery life is a tr ademark of cypress semiconductor. all product and company names mentioned in this document are the trademarks of their respective holders. a 1 a1 corner 0.75 0.75 ?0.300.05(48x) ?0.25 m c a b ?0.05 m c b a 0.15(4x) 0.210.05 1.00 max c seating plane 0.55 max. 0.25 c 0.10 c a1 corner top view bottom view 2 3 4 3.75 5.25 b c d e f g h 65 46 5 23 1 d h f g e c b a 6.000.10 8.000.10 a 8.000.10 6.000.10 b 1.875 2.625 0.26 max. 51-85150-*d [+] feedback [+] feedback
cy62157ev18 mobl ? document #: 38-05490 rev. *d page 11 of 12 document history document title: cy62157ev18 mobl ? 8-mbit (512k x 16) static ram document number:38-05490 rev. ecn no. issue date orig. of change description of change ** 202862 see ecn aju new data sheet *a 291272 see ecn syt converted from ad vance information to preliminary changed v cc max from 2.20 to 2.25 v changed v cc stabilization time in footnote #7 from 100 s to 200 s changed i ccdr from 4 to 4.5 a changed t oha from 6 ns to 10 ns for both 35 ns and 45 ns speed bins changed t doe from 15 and 22 ns to 18 and 22 ns for the 35 and 45 ns speed bins respectively changed t hzoe , t hzbe and t hzwe from 12 and 15 ns to 15 and 18 ns for the 35 and 45 ns speed bins respectively changed t hzce from 12 and 15 ns to 18 and 22 ns for the 35 and 45 ns speed bins respectively changed t sce , t aw, and t bw from 25 and 40 ns to 30 and 35 ns for the 35 and 45 ns speed bins respectively changed t sd from 15 and 20 ns to 18 and 22 ns for the 35 and 45 ns speed bins respectively added pb-free package information *b 444306 see ecn nxr converted from preliminary to final removed 35 ns speed bin removed ?l? bin changed ball e3 from dnu to nc removed redundant footnote on dnu modified maximum ratings spec for supply voltage and dc input voltage from 2.4v to 2.45v changed the i cc typ value from 16 ma to 18 ma and i cc max value from 28 ma to 25 ma for test condition f = fax = 1/t rc changed the i cc max value from 2.3 ma to 3 ma for test condition f = 1mhz changed the i sb1 and i sb2 max value from 4.5 a to 8 a and typ value from 0.9 a to 2 a respectively updated thermal resistance table changed test load capacitance from 50 pf to 30 pf added typ value for i ccdr changed the i ccdr max value from 4.5 a to 3 a corrected t r in data retention characteristics from 100 s to t rc ns changed t lzoe from 3 to 5 changed t lzce from 6 to 10 changed t hzce from 22 to 18 changed t lzbe from 6 to 5 changed t pwe from 30 to 35 changed t sd from 22 to 25 changed t lzwe from 6 to 10 added footnote #13 updated the ordering information and replaced the package name column with package diagram *c 571786 see ecn vkn replaced 45ns speed bin with 55ns [+] feedback [+] feedback
cy62157ev18 mobl ? document #: 38-05490 rev. *d page 12 of 12 *d 908120 see ecn vkn added footnote #7 related to i sb2 added footnote #12 related ac timing parameters document title: cy62157ev18 mobl ? 8-mbit (512k x 16) static ram document number:38-05490 rev. ecn no. issue date orig. of change description of change [+] feedback [+] feedback

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